Compensation circuit and test apparatus

ABSTRACT

Provided is a correction circuit for generating an output signal emphasizing a predetermined signal component of a supplied input signal, including: a first detection section that detects a waveform of the input signal; an amplifying section that amplifies the waveform detected by the first detection section; a correction signal generating section that generates a correction signal by extracting an alternate current component from the waveform amplified by the amplifying section; and an output signal generating section that superimposes the correction signal on the waveform of the input signal, thereby generating the output signal. The first detection section detects the waveform of the input signal and an inverted waveform thereof, the amplifying section amplifies the waveform and the inverted waveform of the input signal, the correction signal generating section generates a correction signal and an inverted correction signal by extracting an alternate current component respectively of the waveform and the inverted waveform of the input signal amplified by the amplifying section, and the output signal generating section generates a pair of differential signals for the output signal, by superimposing the correction signal on the waveform of the input signal and superimposing the inverted correction signal on the inverted waveform of the input signal.

This is a continuation application of PCT/JP2008/62427 filed on Jul. 9,2008.

BACKGROUND

1. Technical Field

The present invention relates to a correction circuit and a testapparatus. In particular, the present invention relates to a correctioncircuit for generating an output signal emphasizing a predeterminedsignal component of a given input signal, and to a test apparatus fortesting a device under test using the correction circuit.

2. Related Art

A test apparatus for supplying a test signal to a device under test andtesting a signal under measurement outputted from the device under testis considered as a type of apparatuses for testing a device under testsuch as a semiconductor circuit. The acceptability of the device undertest can be determined for example by examining whether a normal signalunder measurement is outputted.

A transfer path for transferring signals is provided between the testapparatus and a device under test. However, a resistance, a capacity,and the like exist in the transfer path, which degrades the signalwaveform. As a means to cope with this problem, a technology is alreadyknown to generate a test signal to be inputted to the device under test,by compensating for the loss in the transfer path of the waveform of thetest signal (see for example Patent Document No. 1). There is also knowna technology to compensate for the loss in the transfer path of thesignal received from the device under test.

-   Patent Document No. 1: Japanese Patent Application Publication No.    2006-337140

One compensation method for loss is to generate a correction signal inaccordance with the waveform of the original signal, and add thegenerated correction signal to the original signal. Such a correctionsignal can be generated by generating a differentiated waveform of theoriginal signal, and amplifying the differentiated waveform inaccordance with the amount of loss in the transfer path.

However, when the amplification factor of the differentiated waveformchanges, the direct current component applied to a correction signaloccasionally also fluctuates. By generating an output signal by adding acorrection signal to an original signal, the direct current component ofthe output signal fluctuates in proportion to the amplification factorof the differentiated waveform, to degrade the direct current voltageaccuracy of the output signal after the correction.

In addition, when compensating for the transfer path loss of adifferential signal, the correction signal is required to be generatedfor each of the non-inversion signal and the inversion signal for thedifferential signal. In such a process, if variations are caused in thedirect current components among correction signals for example due tocharacteristics variation in the elements generating these correctionsignals, the direct current voltage accuracy of the differential signalafter correction will degrade.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein toprovide a correction circuit and a test apparatus, which are capable ofovercoming the above drawbacks accompanying the related art. The aboveand other objects can be achieved by combinations described in theindependent claims. The dependent claims define further advantageous andexemplary combinations of the innovations herein.

According to a first aspect related to the innovations herein, oneexemplary correction circuit for generating an output signal emphasizinga predetermined signal component of a supplied input signal, includes: afirst detection section that detects a waveform of the input signal; anamplifying section that amplifies the waveform detected by the firstdetection section; a correction signal generating section that generatesa correction signal by extracting an alternate current component fromthe waveform amplified by the amplifying section; and an output signalgenerating section that superimposes the correction signal on thewaveform of the input signal, thereby generating the output signal.

According to a first aspect related to the innovations herein, oneexemplary test apparatus includes for testing a device under test,includes: a test signal generating section that generates a test signalto be inputted to the device under test; a correction circuit thatinputs, to the device under test, the test signal generated by the testsignal generating section after emphasizing a predetermined signalcomponent of the test signal; a measurement section that measures asignal under measurement outputted by the device under test according tothe test signal; and a determining section that determines acceptabilityof the device under test based on a measurement result of themeasurement section, where the correction circuit includes: a firstdetection section that detects a waveform of the test signal; anamplifying section that amplifies the waveform detected by the firstdetection section; a correction signal generating section that generatesa correction signal from which an alternate current component of thewaveform amplified by the amplifying section has been extracted; and anoutput signal generating section that superimposes the correction signalon the waveform of the test signal, and inputs a resulting test signalto the device under test.

According to a first aspect related to the innovations herein, anotherexemplary test apparatus for testing a device under test, includes: atest signal generating section that generates a test signal to beinputted to the device under test; a correction circuit that receives asignal under measurement outputted from the device under test accordingto the test signal, and obtains a comparison result on whether a levelof the signal under measurement is larger than a predetermined level, bycompensating for a loss of the signal under measurement in a transferpath; and a determining section that determines acceptability of thedevice under test based on the comparison result obtained by thecorrection circuit, where the correction circuit includes: a firstdetection section that detects a waveform of the signal undermeasurement; an amplifying section that amplifies the waveform detectedby the first detection section; a correction signal generating sectionthat generates a correction signal by extracting an alternate currentcomponent from the waveform amplified by the amplifying section; anoutput signal generating section that superimposes the correction signalon the waveform of the signal under measurement; and a comparison resultgenerating section that generates the comparison result based on thesignal generated by the output signal generating section.

The summary clause does not necessarily describe all necessary featuresof the embodiments of the present invention. The present invention mayalso be a sub-combination of the features described above. The above andother features and advantages of the present invention will become moreapparent from the following description of the embodiments taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary configuration of a correction circuit 200.

FIG. 2 shows an exemplary configuration of an output signal generatingsection 70.

FIG. 3 shows an exemplary operation of the correction circuit 200.

FIG. 4 shows another exemplary waveform of the output signal outputtedfrom the output signal generating section 70.

FIG. 5 shows an exemplary configuration of the correction circuit 100according to an embodiment of the present invention.

FIG. 6 shows an exemplary operation of the correction circuit 100.

FIG. 7 shows another exemplary configuration of a correction signalgenerating section 130.

FIG. 8 shows an exemplary operation of the correction signal generatingsection 130 shown in FIG. 7.

FIG. 9 shows another exemplary configuration of the output signalgenerating section 70.

FIG. 10 shows an exemplary configuration of a test apparatus 300according to an embodiment of the present invention.

FIG. 11 shows another exemplary configuration of the test apparatus 300.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, some embodiments of the present invention will bedescribed. The embodiments do not limit the invention according to theclaims, and all the combinations of the features described in theembodiments are not necessarily essential to means provided by aspectsof the invention.

FIG. 1 shows an exemplary configuration of a correction circuit 200. Thecorrection circuit 200 generates an output signal emphasizing apredetermined signal component of a given input signal. For example, thecorrection circuit 200 may generate an output signal emphasizing analternate current component of the given input signal, so as tocompensate for the attenuation of the input signal in the transfer pathor the like. The correction circuit 200 includes a first detectionsection 210, a correction signal generating section 230, an amplifyingsection 250, and an output signal generating section 70.

The first detection section 210 detects the waveform of an input signalVin. The first detection section 210 in the present example includes atransistor 214, a transistor 218, a transistor 220, a transistor 222, aresistance 212, and a resistance 216. The transistor 214 receives theinput signal Vin at the base terminal thereof, and detects the waveformof the input signal Vin.

The transistor 220 has a collector terminal connected to the emitterterminal of the transistor 214, and a gate terminal thereof is providedwith a predetermined voltage V1. The resistance 212 is connected betweenthe emitter terminal of the transistor 220 and the power source lineVEE. That is, the transistor 220 and the resistance 212 function as acurrent source for providing a current corresponding to the voltage V1.

The transistor 218 receives a predetermined reference voltage Vref atthe base terminal thereof, and provides an emitter current correspondingto the reference voltage Vref. The transistor 218 may be provided inparallel with the transistor 214, and have the same characteristics asthe transistor 214.

The transistor 222 has a collector terminal connected to the emitterterminal of the transistor 218. The gate terminal of the transistor 222is connected to the gate terminal of the transistor 220, and is providedwith a predetermined voltage V1. The resistance 216 is connected betweenthe emitter terminal of the transistor 222 and the power source lineVEE. The transistor 222 may have substantially the same characteristicsas the transistor 220, and the resistance 216 may have substantially thesame resistance value as the resistance 212. With this configuration,the transistor 222 and the resistance 216 provide substantially the samecurrent as the transistor 220 and the resistance 212 do.

The correction signal generating section 230 generates a correctionsignal emphasizing the waveform of the input signal Vin. For example,the correction signal generating section 230 may extract an alternatecurrent component Ia of the input signal Vin detected by the transistor214, and set the alternate current component Ia as the correction signalIa. The correction signal generating section 230 may extract, as thealternate current component Ia, a current signal obtained by chargingand discharging the capacitor 232 by means of the input signal Vin givenby the voltage signal.

The correction signal generating section 230 in the present exampleincludes a capacitor 232 and a resistance 236 that are seriallyconnected, between the emitter terminal of the transistor 214 and theemitter terminal of the transistor 218.

The capacitor 232 passes the alternative current component of theemitter current of the transistor 214. The capacitor 232 may also passthe frequency component of the emitter current of the transistor 214,which is in accordance with the resistance value of the resistance 212,the capacity of the capacitor 232, the resistance value of theresistance 236, and the like. For example, the capacitor 232 may pass adifferentiated waveform of the waveform of the emitter current of thetransistor 214.

Specifically, when the voltage value of the input signal Vin fluctuates,the correction signal generating section 230 provides the current Iacorresponding to the fluctuation of the input signal, from thetransistor 214 to the transistor 218. During this, the transistor 220generates a constant current, and so the emitter current of thetransistor 214 increases corresponding to the current Ia provided to thecorrection signal generating section 230. Likewise, the emitter currentof the transistor 218 decreases corresponding to the current Ia receivedfrom the correction signal generating section 230.

For example, the emitter current that is an addition between thecorrection signal (current Ia) and the constant current generated by thetransistor 220 is supplied to the transistor 214. In addition, theemitter current resulting from subtracting the correction signal(current Ia) from the constant current generated by the transistor 222is supplied to the transistor 218.

The amplifying section 250 amplifies the correction signal by amplifyingthe emitter current of the transistor 214 and of the transistor 218, andsupplies the amplified correction signal to the output signal generatingsection 70. The amplifying section 250 in the present example includes acurrent source 260, a transistor 256, a resistance 252, a transistor258, a resistance 254, a current source 270, a transistor 266, aresistance 262, a transistor 268, and a resistance 264.

The current source 260, the transistor 256, the resistance 252, thetransistor 258, and the resistance 254 amplify the emitter current ofthe transistor 214 to which the correction signal is added, at apredetermined amplification factor, to adjust the amplitude of thecorrection signal. In the present example, the distribution ratio of thecorrection signal (current Ia) between the transistor 256 and thetransistor 258 is adjusted, and the current running to the transistor256 is taken out, thereby generating the correction signal whoseamplitude is adjusted. In this case, the above-mentioned amplificationfactor may be smaller than 1.

The emitter terminal of the transistor 256 is connected to the collectorterminal of the transistor 214, via the resistance 252. The emitterterminal of the transistor 258 is connected to the collector terminal ofthe transistor 214, via the resistance 254 provided in parallel with theresistance 252. The current source 260 is provided between the collectorterminal of the transistor 256 and the power source line VCC. Thecollector terminal of the transistor 258 is connected to the powersource line VCC.

With the stated configuration, by adjusting the voltage V3 provided tothe gate terminal of the transistor 256 and the voltage V2 provided tothe gate terminal of the transistor 258, the ratio of the current Ibwhich runs to the transistor 256, of all the current of the transistor214 can be adjusted. In other words, by adjusting the ratio between thevoltages V2 and V3, the emitter current of the transistor 214 can beprovided to the transistor 256 at an arbitrary amplification factorsmaller than or equal to 1. The amplifying section 250 provides theoutput signal generating section 70 with the current resulting fromsubtracting the current Ib running to the transistor 256 from theconstant current generated by the current source 260, as an invertedcorrection signal I2.

Likewise, the current source 270, the transistor 266, the resistance262, the transistor 268, and the resistance 264 amplify the emittercurrent of the transistor 218, after subtraction of the correctionsignal by the correction signal generating section 230. The connectionrelation between the transistor 218 and the current source 270, thetransistor 266, the resistance 262, the transistor 268, and theresistance 264 in the amplifying section 250 is the same as theconnection relation between the transistor 214 and the current source260, the transistor 256, the resistance 252, the transistor 258, and theresistance 254 in the amplifying section 250.

Note that the gate terminal of the transistor 266 is provided with thevoltage V3, and the gate terminal of the transistor 268 is provided withthe voltage V2. That is, the amplification factor of the correctionsignal Ia adopted by the transistor 266 and the transistor 268 iscontrolled to be substantially the same as the amplification factor ofthe correction signal Ia adopted by the transistor 256 and thetransistor 258. In addition, the amplifying section 250 provides theoutput signal generating section 70 with the current resulting fromsubtracting the current Ic running to the transistor 266 from theconstant current generated by the current source 270, as a correctionsignal I1.

The output signal generating section 70 outputs output signals Vout1 andVout2 that emphasize the waveform of the input signal Vin respectivelybased on the correction signal I1 and its inverted correction signal I2provided from the amplifying section 250. For example, the output signalgenerating section 70 may generate the output signal Vout1 bysuperimposing the waveform of the correction signal I1 on the waveformof the current corresponding to the input signal Vin and then convertingthe resulting current waveform into a voltage waveform. Likewise, theoutput signal Vout2 may be generated by superimposing the waveform ofthe inverted correction signal I2 on the inverted waveform of thecurrent corresponding to the input signal Vin, and then converting theresulting current waveform into a voltage waveform. With the statedconfiguration, in the differential output signal, the generated waveformis compensated for the loss in the transfer path.

FIG. 2 shows an exemplary configuration of the output signal generatingsection 70. The output signal generating section 70 includes a seconddetection section 72 and a superimposing section 86. The seconddetection section 72 detects the input signal Vin, and generates adifferential signal corresponding to the input signal. The seconddetection section 72 in the present example includes a current source74, a current source 76, a first differential transistor 78, a seconddifferential transistor 80, a transistor 82, and a current source 84.

The first differential transistor 78 receives the input signal Vin atthe gate terminal thereof. The second differential transistor 80 isprovided in parallel with the first differential transistor 78, andreceives a reference voltage Vref at the gate terminal thereof. Thecollector terminal of the transistor 82 is connected to the emitterterminal of the first differential transistor 78 and to the emitterterminal of the second differential transistor 80. The gate terminal ofthe transistor 82 is provided with the constant voltage V1, and thecurrent source 84 is provided between the emitter terminal of thetransistor 82 and the power source line VEE.

That is, the transistor 82 defines the summation of the current runningto the first differential transistor 78 and the second differentialtransistor 80. For example, when the input voltage Vin increases, thecurrent running to the first differential transistor 78 increases inproportion to the input voltage Vin. The current running to the seconddifferential transistor 80 decreases in proportion to the currentincrease of the first differential transistor 78. With the statedconfiguration, a differential signal having the waveform of the inputsignal Vin and its inverted waveform can be generated.

The collector terminal of the first differential transistor 78 isconnected to the power source line VCC via the current source 74, andthe collector terminal of the second differential transistor 80 isconnected to the power source line VCC via the current source 76. Thecurrent resulting from subtracting the current running to the firstdifferential transistor 78 from the constant current generated by thecurrent source 74 is transferred to the superimposing section 86, as theinverted waveform Id of the input signal. In addition, the currentresulting from subtracting the current running to the seconddifferential transistor 80 from the constant current generated by thecurrent source 76 is transferred to the superimposing section 86, as thewaveform Ie of the input signal.

The superimposing section 86 emphasizes a predetermined signal componentof the differential signal detected by the second detection section 72,based on the correction signal and the inverted correction signal. Forexample, the superimposing section 86 may generate the output signalVout1 by superimposing the correction signal I1 on the waveform Ie ofthe input signal detected by the second detection section 72. Inaddition, the superimposing section 86 may generate the output signalVout2 by superimposing the inverted correction signal I2 on the invertedwaveform Id of the input signal detected by the second detection section72.

The superimposing section 86 in the present example includes a firstcorrection section 40-1 and a second correction section 40-2. The firstcorrection section 40-1 corrects the waveform Ie of the input signaldetected by the second detection section 72, according to a first mirrorcurrent (correction signal I1). For example, the first correctionsection 40-1 may add the first mirror current I1 to the current waveformIe of the input signal. In addition, the first correction section 40-1may convert the generated current waveform into a voltage waveform, andoutput the voltage waveform.

The second correction section 40-2 corrects the inverted waveform Id ofthe input signal detected by the second detection section 72, accordingto a second mirror current (inverted correction signal I2). For example,the second correction section 40-2 may add the second mirror current I2to the inverted current waveform Id of the input signal. In addition,the second correction section 40-2 may convert the generated currentwaveform into a voltage waveform, and output the voltage waveform.

The first correction section 40-1 includes a transistor 90 and aresistance 94. The transistor 90 runs a current corresponding to thecurrent resulting from adding the non-inverted waveform Ie of the inputsignal and the correction signal I2, which is to be supplied to theemitter terminal. The gate terminal of the transistor 90 is providedwith a constant voltage V4.

The resistance 94 is provided between the collector terminal of thetransistor 90 and the power source line VEE. The resistance 94 generatesa voltage waveform corresponding to the current waveform running to thetransistor 90, and outputs the voltage waveform as the output signalVout1. In the present example, the collector voltage of the transistor90 is outputted as the output signal Vout1. With the statedconfiguration, an output signal emphasizing a predetermined signalcomponent of the waveform of the input signal can be generated.

The second correction section 40-2 includes a transistor 88 and aresistance 92. The transistor 88 is provided in parallel with thetransistor 90. The transistor 88 desirably has substantially the samecharacteristics as the transistor 90. The transistor 88 receives, at theemitter terminal thereof, a current being an addition between theinverted waveform Id of the input signal and the inverted correctionsignal I2. The gate terminal of the transistor 88 is provided with theconstant voltage V4 that is the same voltage supplied to the transistor90.

The resistance 92 is provided between the collector terminal of thetransistor 88 and the power source line VEE. The resistance 92 generatesa voltage waveform corresponding to the current waveform running to thetransistor 88, and outputs the generated voltage waveform as the outputsignal Vout2. In the present example, the collector voltage of thetransistor 88 is outputted as the output signal Vout2. With the statedconfiguration, an output signal emphasizing a predetermined signalcomponent of the inverted waveform of the input signal can be generated.

FIG. 3 shows an exemplary operation of the correction circuit 200. Asdescribed above, the correction circuit 200 is provided with an inputsignal Vin attenuated by the transfer path. For example, as shown inFIG. 3, the high frequency component of the input signal Vin of arectangular wave (shown by a wavy line) is attenuated in the transferpath or the like, into a waveform shown by a solid line.

For example, when the edge timing of the input signal Vin is detected bywhether the level of the input signal Vin is larger than thepredetermined reference value Vref, the loss in the above-mentionedtransfer path causes the error (ΔT1) in the edge timing of the originalinput signal. The correction circuit 200 reduces the error of the edgetiming by compensating for the loss of the input signal.

As described above, the correction signal generating section 230extracts the alternate current component of the input signal Vin, andgenerates the correction signal Ia. The correction signal generatingsection 230 may have a time constant corresponding to the time constantof the transfer path.

The correction signal Ia generated by the correction signal generatingsection 230 and its inverted signal are adjusted to an arbitraryamplitude by the amplifying section 250, to become the correction signalI1 and the inverted correction signal I2. Here, the direct current levelα of the correction signal I1 is ideally equal to the direct currentlevel β of the inverted correction signal I2.

In addition, the second detection section 72 detects the non-invertedwaveform Ie and the inverted waveform Id of the input signal. Thesuperimposing section 86 generates the output signal Vout1 from thecurrent resulting from adding the correction signal I1 to thenon-inverted waveform Ie. In addition, the superimposing section 86generates the output signal Vout2 from the current resulting from addingthe inverted correction signal I2 to the inverted signal Id.

The error (ΔT2) in the edge timing of the original input signal can bereduced by measuring the edge timing of the input signal from thecrosspoint between the explained differential signals (Vout1 and Vout2).However, it is difficult to control the direct current levelsrespectively for the correction signal I1 and the inverted correctionsignal I2 in completely the same manner, due to the characteristicsvariations for each transistor and resistance in the first detectionsection 210 and the amplifying section 250. Moreover, as a result ofchanging the amplification factor in the amplifying section 250, thedifference in direct current level between the correction signal I1 andthe inverted correction signal I2 also fluctuates.

In this case, the direct current level of a signal outputted from theoutput signal generating section 70 fluctuates according to thefluctuation in difference of direct current level between the correctionsignal I1 and the inverted correction signal I2. This causes the directcurrent error in the output signal.

FIG. 4 shows another exemplary waveform of the output signal outputtedfrom the output signal generating section 70. As explained above, whenthe direct current level α of the correction signal I1 is different fromthe direct current level β of the inverted correction signal I2, theoutput signal causes a direct current component corresponding to thedifference. Therefore, the measurement error (ΔT3) in timing at thecrosspoint or the like also increases.

FIG. 5 shows an exemplary configuration of the correction circuit 100according to an embodiment of the present invention. The correctioncircuit 100 generates an output signal emphasizing a predeterminedsignal component of a given input signal, and includes a first detectionsection 110, an amplifying section 150, a correction signal generatingsection 130, and an output signal generating section 70.

The overview of the correction circuit 100 is explained first. The firstdetection section 110 detects the waveform of the input signal Vin. Thefirst detection section 110 may further detect an inverted waveform ofthe input signal Vin. The amplifying section 150 amplifies the waveformof the input signal Vin detected by the first detection section 110. Inaddition, the amplifying section 150 may amplify the inverted waveformof the input signal Vin and the inverted waveform of the input signalVin respectively.

The correction signal generating section 130 extracts the alternatecurrent component of the waveform of the input signal Vin afteramplification by the amplifying section 150, to generate a correctionsignal. The correction signal generating section 130 may extract thealternate current component of the inverted waveform of the input signalVin after amplification by the amplifying section 150. In this case, thecorrection signal generating section 130 may generate the correctionsignal and the inverted correction signal from the waveform of the inputsignal Vin and its inverted waveform.

For example, the correction signal may be generated from the alternatecurrent component of the waveform of the input signal Vin, or thecorrection signal may be generated from the alternate current componentof the inverted waveform of the input signal Vin. Likewise, the invertedcorrection signal may be generated from the alternate current componentof the inverted waveform of the input signal Vin, or the invertedcorrection signal may be generated from the alternate current componentof the waveform of the input signal Vin.

The output signal generating section 70 superimposes the correctionsignal to the waveform of the input signal Vin, to generate an outputsignal. The output signal generating section 70 may further generate asignal resulting from superimposing the inverted correction signal tothe inverted waveform of the input signal Vin, to generate a pair ofdifferential signals of the output signal.

The correction circuit 200 explained with reference to FIGS. 1-4generates a correction signal having an arbitrary amplitude, bygenerating a correction signal Ia and then amplifying this correctionsignal Ia. Therefore, a direct current error may be caused during theamplification. As opposed to this, the correction circuit 100 in thepresent example generates a correction signal by amplifying the waveformof the detected input signal to adjust the amplitude, and thenextracting the alternate current component of the waveform. Therefore,the direct current component of the correction signal can be eliminated,thereby reducing the direct current error caused due to the elementvariation, the change in amplification factor, or the like.

The first detection section 110 in the present example includes atransistor 114, a transistor 118, a transistor 112, and a current source116. The transistor 114 receives an input signal Vin at the gateterminal thereof. The transistor 118 is provided in parallel with thetransistor 114, and receives the reference voltage Vref at the gateterminal thereof. The collector terminal of the transistor 112 isconnected to the emitter terminal of the transistor 114 and to theemitter terminal of the transistor 118. In addition, the gate terminalof the transistor 112 is provided with a constant voltage V1, and thecurrent source 116 is provided between the emitter terminal of thetransistor 112 and the power source line VEE.

That is, the transistor 112 defines the summation of the current runningto the transistor 114 and the transistor 118. For example, when theinput voltage Vin has increased, the current running to the transistor114 increases in proportion to the input voltage Vin. The currentrunning to the transistor 118 decreases in proportion to the currentincrease of the transistor 114. With the stated configuration, adifferential signal having the waveform of the input signal Vin and itsinverted waveform can be generated.

The amplifying section 150 includes resistances (152, 154, 160),transistors (156, 158), resistances (162, 164, 170), and transistors(166, 168). The resistance 160 and the resistance 170 function as thecurrent source 260 and the current source 270 explained with referenceto FIG. 1. The operation of the amplifying section 150 is the same asthe operation of the amplifying section 250 explained with reference toFIGS. 1-4, and so the explanation thereof is omitted.

The correction signal generating section 130 includes a first capacitor132, a second capacitor 134, a first control wiring 133, a secondcontrol wiring 135, three resistances (136, 138, 140), a referencetransistor 146, a first mirror transistor 142, a second mirrortransistor 144, and a current source 148. The reference transistor 146,the first mirror transistor 142, and the second mirror transistor 144are provided in parallel to each other, and the gate terminals of themare connected to each other. The collector terminal of the referencetransistor 146 is connected to the gate terminal. The three transistorsmay have substantially the same characteristics as each other. That is,the first mirror transistor 142 and the second mirror transistor 144function as a mirror circuit for providing substantially the samecurrent as the current provided to the reference transistor 146.

The resistance 140 is provided between the emitter terminal of thereference transistor 146 and the power source line VCC. The resistance136 is provided between the emitter terminal of the first mirrortransistor 142 and the power source line VCC, and the resistance 138 isprovided between the emitter terminal of the second mirror transistor144 and the power source line VCC. These three resistances may havesubstantially the same resistance value as each other.

The collector terminal of the reference transistor 146 is connected tothe power source line VEE via the current source 148. With the statedconfiguration, the first mirror transistor 142 and the second mirrortransistor 144 are provided with the same first mirror current andsecond mirror current according to a constant reference current definedby the current source 148.

The first capacitor 132 passes the alternate current component of thewaveform of the input signal after amplification by the amplifyingsection 150, to generate a correction signal Ig. The first capacitor 132in the present example is provided between the collector terminal of thetransistor 166 and the emitter terminal of the first mirror transistor142.

The second capacitor 134 passes the alternate current component of theinverted waveform of the input signal after amplification of theamplifying section 150, to generate an inverted correction signal If.The second capacitor 134 in the present example is provided between thecollector terminal of the transistor 156 and the emitter terminal of thesecond mirror transistor 144.

The first control wiring 133 superimposes a correction signal on thefirst mirror current by controlling the emitter potential of the firstmirror transistor 142 based on the correction signal Ig generated by thefirst capacitor 132. The first control wiring 133 in the present exampleconnects the first capacitor 132 to the emitter terminal of the firstmirror transistor 142, to superimpose the correction signal on the firstmirror current.

The second control wiring 135 superimposes an inverted correction signalon the second mirror current by controlling the emitter potential of thesecond mirror transistor 144 based on the inverted correction signal Ifgenerated by the second capacitor 134. The second control wiring 135 inthe present example connects the second capacitor 134 to the emitterterminal of the second mirror transistor 144, to superimpose theinverted correction signal on the second mirror current.

The output signal generating section 70 emphasizes a predeterminedsignal component of the input signal Vin based on the correction signalI1 (first mirror current) and the inverted correction signal I2 (secondmirror current) provided by the correction signal generating section130. The output signal generating section 70 may have the same functionand configuration as those of the output signal generating section 70explained with reference to FIG. 2. However, note that the output signalgenerating section 70 in the present example receives a correctionsignal and an inverted correction signal from the correction signalgenerating section 130, while the output signal generating section 70 inFIG. 2 receives a correction signal and an inverted correction signalfrom the amplifying section 250.

With the stated configuration, the direct current level can be kept thesame (substantially 0) in the correction signal Ig and the invertedcorrection signal If. Since the correction signal Ig and the invertedcorrection signal If are superimposed on the first mirror current and onthe second mirror current controlled to be the same by the currentmirror circuit, the direct current components of the correction signalI2 and the inverted correction signal I1 after superimposition on themirror current can be controlled to be the same with accuracy. Thisreduces the direct current error due to the correction signal I2 and theinverted correction signal I1.

FIG. 6 shows an exemplary operation of the correction circuit 100. Justas in the example of FIG. 3, the correction circuit 100 is provided withan input signal Vin attenuated in the transfer path. The first detectionsection 110 detects the waveform of the input signal Vin. Note that FIG.6 does not draw the inverted waveform of the input signal Vin.

The amplifying section 150 generates waveforms Ib and Ic resulting fromamplifying the amplitudes of the waveform and the inverted waveform ofthe input signal Vin detected by the first detection section 110 at apredetermined amplification factor. Note that the amplification factorfor the waveform of the input signal Vin is the same as theamplification factor for the inverted waveform thereof. Thisamplification factor may be equal to or smaller than 1.

The first capacitor 132 and the second capacitor 134 respectivelyextract the alternate current component of the waveforms Ib and Ic, togenerate the correction signal Ig and the inverted correction signal If.During this process, the direct current component of the respectivesignals will be eliminated, and so the direct current level of thecorrection signal Ig and the inverted correction signal If will besubstantially 0.

Then, the correction signal I1 is generated by superimposing thecorrection signal Ig on the first mirror current, and the invertedcorrection signal I2 is generated by superimposing the invertedcorrection signal If on the second mirror current. Note that the firstmirror current and the second mirror current are controlled to have thesame current value by means of the current mirror circuit. Therefore,the direct current levels of the correction signal I1 and the invertedcorrection signal I2 will be the same as each other.

Thus generated correction signal I1 and inverted correction signal I2are superimposed on a non-inverted signal Ie and an inverted signal Idas shown in FIG. 3, to obtain a differential output signal whose loss inthe transfer path has been compensated for, as shown in FIG. 3. Inaddition, the direct current error due to the correction signal I1 andthe inverted correction signal I2 can be reduced as stated above.

FIG. 7 shows another exemplary configuration of a correction signalgenerating section 130. In contrast to the configuration of thecorrection signal generating section 130 shown in FIG. 5, the correctionsignal generating section 130 includes two first capacitors 132, twosecond capacitors 134, two resistances 140, two reference transistors146, and two current sources 148.

In addition, in the correction signal generating section 130 in FIG. 5,the base terminals of the first mirror transistor 142 and the secondmirror transistor 144 are connected to the base terminal of a commonreference transistor 146, while in the correction signal generatingsection 130 in the present example, the base terminal of the firstmirror transistor 142 is connected to the base terminal of the firstreference transistor 146-1, and the base terminal of the second mirrortransistor 144 is connected to the base terminal of the second referencetransistor 146-2 which is different from the first reference transistor146-1. In addition, each reference transistor 146 is connected to aresistance 140 and a current source 148, just as the referencetransistor shown in FIG. 5.

The first capacitor 132-1 is provided between the amplifying section 150and the emitter terminal of the first mirror transistor 142. The firstcapacitor 132-2 is provided between the amplifying section 150 and thegate terminal of the second mirror transistor 144. The first capacitors132-1 and 132-2 may be the same as the first capacitor 132 explainedwith reference to FIG. 5.

The second capacitor 134-1 is provided between the amplifying section150 and the emitter terminal of the second mirror transistor 144. Thesecond capacitor 134-2 is provided between the amplifying section 150and the gate terminal of the first mirror transistor 142. The secondcapacitors 134-1 and 134-2 may be the same as the second capacitor 134explained with reference to FIG. 5.

The first control wiring 133 controls, based on the correction signalIg, the base voltage of each of the first reference transistor 146-1 andthe first mirror transistor 142, and the emitter voltage of the secondmirror transistor 144. For example, the first control wiring 133 maycontrol the base voltage and the emitter voltage mentioned above, bychanging, according to the correction signal Ig, the base current ofeach of the first reference transistor 146-1 and the first mirrortransistor 142 and the emitter current of the second mirror transistor144.

Likewise, the second control wiring 135 controls, based on the invertedcorrection signal If, the base voltage of each of the second referencetransistor 146-2 and the second mirror transistor 144, and the emittervoltage of the first mirror transistor 142. For example, the secondcontrol wiring 135 may control the base voltage and the emitter voltagementioned above, by changing, according to the inverted correctionsignal If, the base current of each of the second reference transistor146-2 and the second mirror transistor 144 and the emitter current ofthe first mirror transistor 142.

FIG. 8 shows an exemplary operation of the correction signal generatingsection 130 shown in FIG. 7. In the amplifying section 150, theamplification factors for waveform of an input signal and its invertedwaveform are defined in the ratio between the common voltages V2 and V3and therefore are ideally the same as each other. Therefore, in theconfiguration of the correction signal generating section 130 explainedwith reference to FIG. 5, the amplitudes of the correction signal Ig andthe inverted correction signal If, outputted from the first capacitor132 and the second capacitor 134, become the same as each other, asshown in FIG. 6.

However, the amplification factor of the waveform of an input signal andthe amplification factor of its inverted waveform may occasionally bedifferent from each other, due to variations of element characteristicsin the amplifying section 150. If this happens, the amplitude A1 of thecorrection signal Ig and the amplitude A2 of the inverted correctionsignal If, added to the first mirror current and the second mirrorcurrent, will be different from each other.

In contrast, with the configuration stated with reference to FIG. 7, thecorrection signal generating section 130 in the present example adds thesummation between the correction signal Ig and the inverted correctionsignal If to the first mirror current I1. In addition, the summationbetween the correction signal Ig and the inverted correction signal Ifis subtracted from the second mirror current I2. Therefore even when theamplitude A1 of the correction signal Ig and the amplitude A2 of theinverted correction signal If are different from each other, theamplitudes of the correction signal and the inverted correction signaladded to the first mirror current I1 and the second mirror current I2can be equal to each other. Consequently, it becomes possible toemphasize a signal component in a differential signal more accurately.

FIG. 9 shows another exemplary configuration of the output signalgenerating section 70. The output signal generating section 70 in thepresent example includes a second detection section 72 and asuperimposing section 86. The configuration of the superimposing section86 may be the same as the configuration of the superimposing section 86explained with reference to FIG. 2.

The second detection section 72 in the present example is different fromthe superimposing section 86 explained with reference to FIG. 2, in thatit does not include a current source 74 or a current source 76. Thefirst differential transistor 78, the second differential transistor 80,the transistor 82, and the current source 84 may be the same as thefirst differential transistor 78, the second differential transistor 80,the transistor 82, and the current source 84 explained with reference toFIG. 2. Note that the collector terminal of the first differentialtransistor 78 is connected to the second mirror transistor 144, and thecollector terminal of the second differential transistor 80 is connectedto the first mirror transistor 142.

With the stated configuration, the current is provided to the firstdifferential transistor 78 and the second differential transistor 80,from the first mirror transistor 142 and the second mirror transistor144. That is, the current source 74 and the current source 76 areeliminated, to reduce the circuit size.

FIG. 10 shows an exemplary configuration of a test apparatus 300according to an embodiment of the present invention. The test apparatus300 tests a device under test 400 such as a semiconductor chip, andincludes a test signal generating section 310, a correction circuit 340,and a determining section 350. The test apparatus 300 is electricallyconnected to the device under test 400, by means of a transfer path 360including a pattern wiring, a cable, or the like.

The test signal generating section 310 generates a test signal to beinputted to the device under test 400, and inputs the test signal viathe transfer path 360. For example, the test signal generating section310 inputs, to the device under test 400, a test signal including apredetermined logical pattern, and causes the device under test 400 tooperate according to the logical pattern.

The test signal generating section 310 includes a pattern generator 320and a waveform shaper 330. The pattern generator 320 executes a testprogram provided from a user or the like, to generate a logical patternto be included in a test signal. The waveform shaper 330 shapes thewaveform of the test signal that includes the logical pattern generatedby the pattern generator 320.

The device under test 400 operates according to the inputted testsignal, to output a signal under measurement corresponding to theoperation result. For example, the device under test 400 may include adigital circuit operating according to a test signal, or a memorycircuit outputting data of an address corresponding to a test signal.

The correction circuit 340 receives the signal under measurementoutputted from the device under test 400 in response to a test signal,and obtains a comparison result on whether the level of the signal undermeasurement is larger than a predetermined reference level, bycompensating for the loss of the signal under measurement in thetransfer path. The correction circuit 340 may be the same as either thecorrection circuit 100 or the correction circuit 200 explained abovewith reference to FIGS. 1-9.

The correction circuit 340 in the present example receives a signalunder measurement, as an input signal explained with reference to FIGS.1-9. The reference level in the present example may be a middle levelbetween the voltage level of the L logic and the voltage level of the Hlogic in the signal under measurement. The correction circuit 340 maysupply, to the determining section 350, the output signal explained withreference to FIGS. 1-9, as a comparison result.

The determining section 350 determines the acceptability of the deviceunder test 400 based on the comparison result obtained by the correctioncircuit 340. For example, the determining section 350 may sequentiallydetect the logical values of the supplied comparison result, at thetimings of the supplied clock signal. The acceptability of the deviceunder test 400 may be determined by comparing the detected logicalpattern with the expected logical pattern. The expected logical patternmay be generated by the pattern generator 320 based on the logicalpattern of the test signal.

The test apparatus 300 in the present example can measure a signal undermeasurement, by emphasizing a predetermined signal component of thesignal under measurement to compensate for the loss of it in thetransfer path 360. Consequently, the effect of the transfer path 360 ina test can be decreased, to be able to conduct a test of thecharacteristics of the implementation state of the device under test 400with accuracy. Note that the characteristics of each element of thecorrection circuit 340 may be set according to the characteristics ofthe transfer path 360.

FIG. 11 shows another exemplary configuration of the test apparatus 300.In contrast to the configuration of the test apparatus 300 shown in FIG.10, the test apparatus 300 in the present example further includes ameasurement section 370. Moreover, the correction circuit 340 isprovided between a test signal generating section 310 and a transferpath 360, and emphasizes a predetermined signal component of a testsignal.

The measurement section 370 measures a signal under measurement receivedfrom a device under test 400. For example, the measurement section 370may output a comparison result showing which of the signal level of thesignal under measurement and a predetermined reference level is larger.The determining section 350 determines the acceptability of the deviceunder test 400 based on the comparison result of the measurement section370.

With the stated configuration, a test of the device under test 400 canbe pursued using a test signal whose loss in the transfer path 360 hasbeen compensated for in advance. As a result, the device under test 400can be tested with accuracy. Note that the configuration of FIG. 11 mayfurther include a correction circuit 340, instead of the measurementsection 370. That is, the test apparatus 300 may include a correctioncircuit 340 for supplying, to the device under test 400, a test signalafter emphasizing a predetermined signal component of the test signal,and a correction circuit 340 for measuring a signal under measurement byemphasizing a predetermined signal component. Accordingly, the deviceunder test 400 can be tested with even more accuracy, by compensatingfor both of the losses of the test signal and the signal undermeasurement.

While the embodiments of the present invention have been described, thetechnical scope of the invention is not limited to the above describedembodiments. It is apparent to persons skilled in the art that variousalterations and improvements can be added to the above-describedembodiments. It is also apparent from the scope of the claims that theembodiments added with such alterations or improvements can be includedin the technical scope of the invention.

For example, it is clear that the technical scope of the presentinvention includes an embodiment in which the PNP transistor shown inFIGS. 1-9 is replaced with an NPN transistor, and the NPN transistorshown in FIGS. 1-9 is replaced with a PNP transistor.

The operations, procedures, steps, and stages of each process performedby an apparatus, system, program, and method shown in the claims,embodiments, or diagrams can be performed in any order as long as theorder is not indicated by “prior to,” “before,” or the like and as longas the output from a previous process is not used in a later process.Even if the process flow is described using phrases such as “first” or“next” in the claims, embodiments, or diagrams, it does not necessarilymean that the process must be performed in this order.

As described above, the embodiments of the present invention cancompensate for the loss of a signal in a transfer path. Furthermore,when adjusting the amplification factor of a correction signal foradjusting the loss compensation, the amplification factor of thecorrection signal can be adjusted without causing any direct currenterror. The direct current error due to element variations or the likecan also be eliminated.

What is claimed is:
 1. A correction circuit for generating an outputsignal emphasizing a predetermined signal component of a supplied inputsignal, comprising: a first detection section that detects a waveform ofthe input signal; an amplifying section that amplifies the waveformdetected by the first detection section; a correction signal generatingsection that generates a correction signal by extracting an alternatecurrent component from the waveform amplified by the amplifying section;and an output signal generating section that superimposes the correctionsignal on the waveform of the input signal, thereby generating theoutput signal.
 2. The correction circuit according to claim 1, whereinthe first detection section detects the waveform of the input signal andan inverted waveform thereof, the amplifying section amplifies thewaveform and the inverted waveform of the input signal, the correctionsignal generating section generates a correction signal and an invertedcorrection signal by extracting an alternate current componentrespectively of the waveform and the inverted waveform of the inputsignal amplified by the amplifying section, and the output signalgenerating section generates a pair of differential signals for theoutput signal, by superimposing the correction signal on the waveform ofthe input signal and superimposing the inverted correction signal on theinverted waveform of the input signal.
 3. The correction circuitaccording to claim 2, wherein the output signal generating sectionincludes: a second detection section that detects the waveform of theinput signal and the inverted waveform of the input signal; and asuperimposing section that superimposes the correction signal on thewaveform of the input signal detected by the second detection section,and superimposes the inverted correction signal on the inverted waveformof the input signal detected by the second detection section.
 4. Thecorrection circuit according to claim 3, wherein the correction signalgenerating section includes: a first capacitor that passes an alternatecurrent component of the waveform of the input signal amplified by theamplifying section, thereby generating the correction signal; a secondcapacitor that passes an alternate current component of the invertedwaveform of the input signal amplified by the amplifying section,thereby generating the inverted correction signal; a referencetransistor that provides a predetermined reference current; a firstmirror transistor that provides a first mirror current according to thereference current, a base terminal of the first mirror transistor beingconnected to a base terminal of the reference transistor; a secondmirror transistor that provides a second mirror current according to thereference current, a base terminal of the second mirror transistor beingconnected to the base terminal of the reference transistor; a firstcontrol wiring that superimposes the correction signal on the firstmirror current by controlling an emitter potential of the first mirrortransistor based on the correction signal; and a second control wiringthat superimposes the inverted correction signal on the second mirrorcurrent by controlling an emitter potential of the second mirrortransistor based on the inverted correction signal, and thesuperimposing section includes: a first correction section that correctsthe waveform of the input signal detected by the second detectionsection, according to the first mirror current; and a second correctionsection that corrects the inverted waveform of the input signal detectedby the second detection section, according to the second mirror current.5. The correction circuit according to claim 4, wherein the seconddetection section includes a first differential transistor and a seconddifferential transistor that detect the waveform and the invertedwaveform of the input signal, one of the first and second differentialtransistors is connected to the first mirror transistor, and the otherof the first and second differential transistors is connected to thesecond mirror transistor.
 6. The correction circuit according to claim3, wherein the correction signal generating section includes: a firstcapacitor that passes an alternate current component of the waveform ofthe input signal amplified by the amplifying section, thereby generatingthe correction signal; a second capacitor that passes an alternatecurrent component of the inverted waveform of the input signal amplifiedby the amplifying section, thereby generating the inverted correctionsignal; a first reference transistor that provides a predeterminedreference current; a first mirror transistor that provides a firstmirror current according to the reference current provided by the firstreference transistor, a base terminal of the first mirror transistorbeing connected to a base terminal of the first reference transistor; asecond reference transistor that provides a predetermined referencecurrent; a second mirror transistor that provides a second mirrorcurrent according to the reference current provided by the secondreference transistor, a base terminal of the second mirror transistorbeing connected to a base terminal of the second reference transistor; afirst control wiring that controls, based on the correction signal, abase voltage of the first reference transistor and the first mirrortransistor and an emitter voltage of the second mirror transistor; and asecond control wiring that controls, based on the inverted correctionsignal, a base voltage of the second reference transistor and the secondmirror transistor and an emitter voltage of the first mirror transistor,and the superimposing section includes: a first correction section thatcorrects the waveform of the input signal detected by the seconddetection section, according to the first mirror current; and a secondcorrection section that corrects the inverted waveform of the inputsignal detected by the second detection section, according to the secondmirror current.
 7. The correction circuit according to claim 1, whereinthe first detection section detects a waveform and an inverted waveformof the input signal, the amplifying section amplifies the waveform andthe inverted waveform of the input signal detected by the firstdetecting section, the correction signal generating section generates(i) a first correction mirror current in which the correction signal issuperimposed on a first mirror current according to a predeterminedreference current and (ii) a second correction mirror current in whichan inverted correction signal according to an alternate currentcomponent extracted from the inverted waveform of the input signalamplified by the amplifying section is superimposed on a second mirrorcurrent according to the reference current, and the output signalgenerating section superimposes the first correction mirror current onthe waveform of the input signal and superimposes the second correctionmirror current on the inverted waveform, thereby generating a pair ofdifferential signals of the output signal.
 8. The correction circuitaccording to claim 7, wherein the correction signal generating sectionincludes: a reference transistor that provides the reference current; afirst mirror transistor, a base terminal of the first mirror transistorbeing connected to a base terminal of the reference transistor; and asecond mirror transistor, a base terminal of the second mirrortransistor being connected to the base terminal of the referencetransistor.
 9. The correction circuit according to claim 8, wherein theoutput signal generating section includes: a second detection sectionthat detects the waveform of the input signal and the inverted waveformof the input signal; and a superimposing section that superimposes thecorrection signal on the waveform of the input signal detected by thesecond detection section, and superimposes the inverted correctionsignal on the inverted waveform of the input signal detected by thesecond detection section.
 10. The correction circuit according to claim9, wherein the first mirror transistor provides a first mirror currentaccording to the reference current, the second mirror transistorprovides a second mirror current according to the reference current, thecorrection signal generating section further includes: a first capacitorthat passes an alternate current component of the waveform of the inputsignal amplified by the amplifying section, thereby generating thecorrection signal; a second capacitor that passes an alternate currentcomponent of the inverted waveform of the input signal amplified by theamplifying section, thereby generating the inverted correction signal; afirst control wiring that superimposes the correction signal on thefirst mirror current by controlling an emitter potential of the firstmirror transistor based on the correction signal; and a second controlwiring that superimposes the inverted correction signal on the secondmirror current by controlling an emitter potential of the second mirrortransistor based on the inverted correction signal, and thesuperimposing section includes: a first correction section that correctsthe waveform of the input signal detected by the second detectionsection, according to the first mirror current; and a second correctionsection that corrects the inverted waveform of the input signal detectedby the second detection section, according to the second mirror current.11. The correction circuit according to claim 9, wherein the seconddetection section includes a first differential transistor and a seconddifferential transistor that detect the waveform and the invertedwaveform of the input signal, one of the first and second differentialtransistors is connected to the first mirror transistor, and the otherof the first and second differential transistors is connected to thesecond mirror transistor.
 12. The correction circuit according to claim7, wherein the correction signal generating section includes: a firstreference transistor that provides the reference current; a secondreference transistor that provides the reference current; a first mirrortransistor, a base terminal of the first mirror transistor beingconnected to a base terminal of the first reference transistor; and asecond mirror transistor, a base terminal of the second mirrortransistor being connected to a base terminal of the second referencetransistor.
 13. The correction circuit according to claim 12, whereinthe output signal generating section includes: a second detectionsection that detects the waveform of the input signal and the invertedwaveform of the input signal; and a superimposing section thatsuperimposes the correction signal on the waveform of the input signaldetected by the second detection section, and superimposes the invertedcorrection signal on the inverted waveform of the input signal detectedby the second detection section.
 14. The correction circuit according toclaim 13, wherein the first mirror transistor provides a first mirrorcurrent according to the reference current, the second mirror transistorprovides a second mirror current according to the reference current, thecorrection signal generating section further includes: a first capacitorthat passes an alternate current component of the waveform of the inputsignal amplified by the amplifying section, thereby generating thecorrection signal; a second capacitor that passes an alternate currentcomponent of the inverted waveform of the input signal amplified by theamplifying section, thereby generating the inverted correction signal; afirst control wiring that controls, based on the correction signal, abase voltage of the first reference transistor and the first mirrortransistor and an emitter voltage of the second mirror transistor; and asecond control wiring that controls, based on the inverted correctionsignal, a base voltage of the second reference transistor and the secondmirror transistor and an emitter voltage of the first mirror transistor,and the superimposing section includes: a first correction section thatcorrects the waveform of the input signal detected by the seconddetection section, according to the first mirror current; and a secondcorrection section that corrects the inverted waveform of the inputsignal detected by the second detection section, according to the secondmirror current.
 15. The correction circuit according to claim 13,wherein the second detection section includes a first differentialtransistor and a second differential transistor that detect the waveformand the inverted waveform of the input signal, one of the first andsecond differential transistors is connected to the first mirrortransistor, and the other of the first and second differentialtransistors is connected to the second mirror transistor.
 16. A testapparatus for testing a device under test, comprising: a test signalgenerating section that generates a test signal to be inputted to thedevice under test; a correction circuit that inputs, to the device undertest, the test signal generated by the test signal generating sectionafter emphasizing a predetermined signal component of the test signal; ameasurement section that measures a signal under measurement outputtedby the device under test according to the test signal; and a determiningsection that determines acceptability of the device under test based ona measurement result of the measurement section, wherein the correctioncircuit includes: a first detection section that detects a waveform ofthe test signal; an amplifying section that amplifies the waveformdetected by the first detection section; a correction signal generatingsection that generates a correction signal from an alternate currentcomponent of the waveform amplified by the amplifying section; and anoutput signal generating section that superimposes the correction signalon the waveform of the test signal, and inputs a resulting test signalto the device under test.
 17. The test apparatus according to claim 16,wherein the first detection section detects a waveform and an invertedwaveform of the test signal, the amplifying section amplifies thewaveform and the inverted waveform of the test signal detected by thefirst detecting section, the correction signal generating sectiongenerates (i) a first correction mirror current in which the correctionsignal is superimposed on a first mirror current according to apredetermined reference current and (ii) a second correction mirrorcurrent in which an inverted correction signal according to an alternatecurrent component extracted from the inverted waveform of the testsignal amplified by the amplifying section is superimposed on a secondmirror current according to the reference current, and the output signalgenerating section superimposes the first correction mirror current onthe waveform of the test signal and superimposes the second correctionmirror current on the inverted waveform, and inputs a resulting testsignal to the device under test.
 18. A test apparatus for testing adevice under test, comprising: a test signal generating section thatgenerates a test signal to be inputted to the device under test; acorrection circuit that receives a signal under measurement outputtedfrom the device under test according to the test signal, and obtains acomparison result on whether a level of the signal under measurement islarger than a predetermined level, by compensating for a loss of thesignal under measurement in a transfer path; and a determining sectionthat determines acceptability of the device under test based on thecomparison result obtained by the correction circuit, wherein thecorrection circuit includes: a first detection section that detects awaveform of the signal under measurement; an amplifying section thatamplifies the waveform detected by the first detection section; acorrection signal generating section that generates a correction signalby extracting an alternate current component from the waveform amplifiedby the amplifying section; an output signal generating section thatsuperimposes the correction signal on the waveform of the signal undermeasurement; and a comparison result generating section that generatesthe comparison result based on the signal generated by the output signalgenerating section.
 19. The test apparatus according to claim 18 whereinthe first detection section detects a waveform and an inverted waveformof the signal under measurement, the amplifying section amplifies thewaveform and the inverted waveform of the signal under measurementdetected by the first detection section, the correction signalgenerating section generates (i) a first correction mirror current inwhich the correction signal is superimposed on a first mirror currentaccording to a predetermined reference current and (ii) a secondcorrection mirror current in which an inverted correction signalaccording to an alternate current component extracted from the invertedwaveform of the signal under measurement amplified by the amplifyingsection is superimposed on a second mirror current according to thereference current, and the output signal generating section superimposesthe first correction mirror current on the waveform of the signal undermeasurement and superimposes the second correction mirror current on theinverted waveform.